1. Filed of the Invention
The present invention generally relates to methods and circuits for delaying a reference clock signal to obtain a delayed clock signal which is delayed relative to the reference clock signal, and more particularly, the present invention relates to delay locked loop (DLL) circuits and methods.
2. Description of the Related Art
A delay locked loop (DLL) circuit functions to delay a reference clock signal by a preset time period to thereby generate a delayed clock signal which is delayed relative to the reference clock signal. The generation of delayed clock signals is generally necessary in certain circuits which exhibit relatively high integration densities and which are synchronized with external clock signals. Such circuits include Rambus DRAMs (RDRAMs) and Synchronous DRAMs (SDRAMs).
Generally, external clock signals are supplied via an input pin of a semiconductor integrated circuit, and from there they are distributed to various component parts of the circuit. A clock signal arriving at a component part which is located relatively far from the input pin may be considerably delayed compared to the same clock signal arriving at a component part directly adjacent the input pin. As such, as clock frequency increases, it becomes more and more difficult to maintain synchronization between the various component parts of the semiconductor integrated circuit. Also, the delay of the clock signal can deteriorate the high frequency operation of the semiconductor integrated circuit. That is, the time period needed to output data (output data access time) is increased.
Particularly in an effort to facilitate synchronization of components, the semiconductor integrated circuit may be equipped with a DLL circuit which receives the external clock signals and generates internal clock signals that are delayed for a predetermined period of time relative to the external clock signals. These delayed internal clock signals are selectively supplied as clock signals to the respective component parts of the semiconductor integrated circuit.
FIG. 1 is a block diagram of a conventional register-controlled DLL (RDLL). As shown, an external clock signal CLKin is delayed by a delay line 13 to produce an internal clock signal CLKout which is delayed relative to the external clock signal CLKin. The delay line 13 includes a plurality of unit delay circuits (not shown) which are selectively made operational in response to respective control signals S1 through Sn. An amount of delay of the internal clock signal CLKout relative to the external clock signal CLKin depends on a number of the unit delay circuits which are effectively enabled by the control signals S1 through Sn.
A delay compensator 17 outputs a signal CLKoutxe2x80x2 based on an input internal signal CLKout. A phase detector 11 detects a phase difference between the signal CLKoutxe2x80x2 and the external clock signal CLKin, and generates a shift right (SR) signal or a shift left (SL) signal based on the phase of the internal signal CLKout (or signal CLKoutxe2x80x2) relative to that of the external signal CLKin. In particular, an SR signal is generated when the internal signal CLKout lags behind the external signal CLKin, and a SL signal is generated when the internal signal CLKout leads the external signal CLKin.
A control circuit 15 (which is essentially a shift register) shifts the output control signals S1 through Sn in a direction which is responsive to the SR signal or the SL signal. In this manner, the number of unit delay circuits which are enabled in the delay line 13 is varied based on variations in the values of the control signals S1 through Sn. As such, the delay time of the delay line 13 is varied based on the phase difference between the external clock signal CLKin and the internal clock signal CLKout.
FIG. 2 shows the relationship between a clock period tCC of an operational clock and a delay time td of the unit delay circuits in the conventional DLL of FIG. 1. The illustrated relationships are based on a synchronous DRAM in which a CAS latency (CL) is 3 when the frequency of an operational clock is within the range of 166 MHz-200 MHz, the CL is 4 when the frequency of the operational clock is within the range of 200 MHz-250 MHz, and the CL is 5 when the frequency of the operational clock is within the range of 250 MHz-300 MHz.
Generally, the DLL circuit must have a wide locking range to operate within a wide frequency range. In addition, the DLL circuit must include a sufficient number of unit delay circuits each having a minute delay time in order to achieve a fine locking resolution, particularly in a high-frequency domain.
The delay time td of a unit delay circuit effectively defines the locking resolution. For example, to obtain a specified locking resolution in the high-frequency domain (CL=5), the delay time td of the unit delay circuits may be designed to be ⅙ of a nanosecond (ns). In this case, as shown in FIG. 2, there must be at least 36 unit delay circuits in the delay line 13 of FIG. 1 to guarantee operation in the low-frequency domain (CL=3). As such, while the locking resolution is ⅙ ns in the low-frequency domain (CL=3), the worst case locking time is 36 cycles. As such, the locking time becomes undesirably long.
On the one hand, the delay time of the unit delay circuits should be relatively long when operating in the low-frequency domain, to thereby reduce the number of cycles of the worst case locking time. On the other hand, the delay time of the unit delay circuits must be made relatively short when operating in the high-frequency domain to achieve the necessary locking resolution, and accordingly, the number of cycles of the worst case locking time in the low frequency domain is unavoidably increased. In other words, locking time in a low frequency domain (CL=3) is increased if the unit delay time td is shortened to increase resolution in a high-frequency domain (CL=5).
According to one aspect of the present invention, a delay locked loop circuit for a memory device is provided in which a delay line receives an input clock signal and includes a cascaded plurality of unit delay circuits. An adjustment circuit varies a delay time of the unit delay circuits according to a column-address-strobe (CAS) latency of the memory device. A phase detector detects a phase difference between the input clock signal and an output clock signal of the delay line, and a control circuit which controls an enabled state of the unit delay circuits according to an output of said phase detector.
According to another aspect of the present invention, a delay locked loop method for a memory device is provided which includes delaying an input clock signal to obtain a delayed clock signal by passing the input clock signal through a delay line having a cascaded plurality of unit delay circuits, controlling an enabled state of each of the unit delay circuits according to a phase difference between the input clock signal and delayed clock signal, and varying a delay time of the unit delay circuits according to a column-address-strobe (CAS) latency of the memory device.
According to still another aspect of the present invention, a delay locked loop circuit for a memory device is provided in which a delay line receives an input clock signal and includes a cascaded plurality of unit delay circuits. A shift register circuit having plural circuit stages outputs parallel control signals to the unit delay circuits, respectively, wherein the parallel control signals constitute a multi-bit output of the shift register circuit. Both a direction and a number of stages of each bit-shift operation of the shift register circuit are variable. A phase detector detects a phase difference between the input clock signal and an output clock signal of the delay line, and the direction of the bit-shift operation of the shift register circuit is controlled by an output of the phase detector. A number of stages of the bit-shift operation of the shift register circuit is controlled by a column address strobe (CAS) latency of the memory device.
According to yet another aspect of the present invention, a delay locked loop method for a memory device is provided which includes delaying an input clock signal to obtain a delayed clock signal by passing the input clock signal through a delay line having a cascaded plurality of unit delay circuits, generating a multi-bit control signal which controls an enabled state of each of the plurality of unit delay circuits, and bit-shifting the multi-bit control signal in a direction corresponding to a phase difference between the input clock signal and delayed clock signal, and by a number of bits corresponding to a column address strobe (CAS) latency of the memory device.